Secure Processor Design by RISC-V Framework
Project ID:
P11_20
Principal Investigator:
Dr. Yunsi Fei
Email:
Co-Principal Investigator(s):
Prof. David Kaeli
Topic Areas:
Design
Abstract
The recent discovered exploits, Meltdown and Spectre, have exposed the fundamental pitfall of modern computer architecture – numerous performance features and microarchitectures have become security vulnerabilities, especially for information exfiltration across logic boundaries, e.g., user vs. kernel space boundary, host vs. enclave boundaries, etc. This project adopts the secure-by-design principle and proposes to design secure and high-performance open processor architecture based on the RISC-V framework. Associated with the processor design, we will also develop a microarchitecture software simulator and provide proof of security for our design.