Current computing platforms leverage different forms of encryption or secure enclaves to guard sensitive data and protect against information leakage. But we continue to read reports that our computing devices are susceptible to side-channel attacks and information leakage. In addition to these vulnerabilities, with the advent of quantum computing, large-scale quantum computers pose a threat to the reliability of current public-key cryptosystems, necessitating the need for quantum-proof cryptographic systems. Lattice-based cryptography has been shown to be a promising framework for both post-quantum cryptography and Fully Homomorphic Encryption (FHE) [1]. Lattice-based FHE enables users to securely outsource both the storage and computation of sensitive data to untrusted servers. Although FHE offers a high degree of security, it suffers from prohibitively large computational costs. The primary bottleneck in lattice-based cryptography is polynomial multiplication. For lattice-based FHE to become viable for real-world systems, we need a highly efficient and scalable implementation of polynomial multiplication.

In this project we propose to characterize FPGA-based and GPU-based implementations of polynomial multiplication targeting its two major computationally-expensive operations: modular reduction and the Number Theoretic Transform (NTT). Our work will explore modular reduction and analyze several variants of the widely-used Barrett modular reduction algorithm [21]. Our focus is to consider a heterogeneous hardware/software targeting accelerator hardware that can effectively reduce the high cost of polynomial multiplication.