In this project, we propose to develop a cost-effective mechanism for protecting sensitive hardware intellectual property through hybrid ASIC/Programmable integrated circuit design. In contrast with the use of eFPGAs or other Look-Up Table (LUT-) based solutions, which incur intolerable area, power and performance overhead and which require external storage and loading of the configuration bitstream upon power-on, this project takes a different approach: based on the observation that existing solutions may be an overkill, we start with a state-of-the-art Transistor-Level Programmable (TRAP) fabric, which PI Sechen and Co-PI Makris developed previously for the purpose of IC redaction, and we seek to explore the trade-off between fine-grain programmability and ability to withstand bitstream retrieval attacks. Moreover, leveraging Co-PI Friedman’s expertise in spintronics, we seek to replace the SRAM memory that is currently employed in TRAP with MRAM. Besides dramatically reducing the required overhead, the proposed fine-grained hybrid CMOS/MRAM implementation of TRAP also offers the option of non-volatile bitstream storage, thereby simplifying IC operation. Successful design of this hybrid CMOS/MRAM design in the first year of this project will lead to a request for an extension in order to tape-out this fabric at a compatible technology and demonstrate it in silicon.