Built upon the research findings of this project in Year 1 & Year 2, this research in Year 3 proposes a new method to reduce the size of neural networks for side-channel attacks in the cross-device setting. In the cross-device setting, training power traces are from one device while test power traces are from a different device. It is a more realistic attack setting than the single-device setting primarily investigated in existing studies. Distribution shifts between training traces and test traces can be introduced by discrepancies in keys, hardware, software, and acquisition setups between two devices. In Year 1, we have developed two methods based on transfer learning, including triplet networks and adversarial domain adaptation, to successfully improve the accuracy of deep-learning side-channel attacks in the cross-device scenario. In other words, we answered the question “How to transfer?” in Year 1. In Year 2, we focus on investigating various software discrepancies and developing methods to quantify distribution shifts caused by hardware and software discrepancies.

Despite promising results in Year 1 and Year 2, the neural networks we developed for side-channel attacks are complex, which requires millions of parameters and several hours (even days) to train on a GPU machine. This raises significant challenges for deploying a neural network on an embedded or mobile device to perform side-channel attacks. In other words, the current neural networks are not portable. To tackle the above limitation in Year 3, the team proposes a new pruning algorithm to reduce the size of neural networks but still be able to effectively recover keys. In addition to size reduction, pruning can also reduce training time and memory usage, which allows a resource-constrained device, such as a Raspberry Pi, to run testing (and even training) of deep-learning side-channel attacks. We will implement the proposed method and conduct comprehensive evaluations by examining both power and EM (electromagnetic) traces on multiple targets, including microcontrollers (8-bit AVR XMEGA and 32-bit ARM STM32F3) and FPGAs (Xilinx Artix-7), running AES-128 encryption using ChipWhisperer platform. Large-scale datasets, source code, and publications will be shared with CHEST industry partners.