This research aims to develop synthesis algorithms for secure and efficient polymorphic logic circuits. Polymorphic gates can implement multiple Boolean functions where the functionality is determined statically or dynamically based on internal/external control signals. A polymorphic circuit consists of both polymorphic gates and traditional monomorphic gates. Polymorphic circuits promise significant area, power, performance, and security advantages over conventional logic circuits. Each of these benefits have been demonstrated in recent years on small circuits via simulation/analytical studies and selective implementations. However, for a comprehensive evaluation and demonstration of these benefits for larger, more practical circuits, it is essential to develop synthesis methods to automatically generate polymorphic logic circuits from RTL descriptions while exploring PPA1 and security tradeoffs.

This research will develop (1) abstract models of polymorphic gates, (2) PPA models of polymorphic gates and control circuits, (3) synthesis algorithms for polymorphic circuits to meet PPA and security constraints, and (4) analysis methods to compare PPA and security of polymorphic circuits with standard logic circuits generated by COTS synthesis tools. Specialized synthesis algorithms will be developed for various types of circuits based on, (1) Mix Allowed: homogeneous vs. heterogeneous, (2) Programming Model: static vs. dynamic, (3) Control Type: individual gates vs. modular vs. global. All models and methods will be evaluated in the context of 10K to 100K gate equivalent designs including ALUs, controllers, and small processors.