Proposed Tasks. Built upon the research findings of this project in the past three years, this proposed research in Year 4 (2024 – 2025) will include two major tasks. In Task 1, we will develop a new method to further reduce the size of neural networks for side-channel attacks. In Task 2, we will investigate the advantages and disadvantages of deep learning side-channel attacks over simulated traces at the RTL (Register Transfer Level) level in the pre-silicon stage.

In Task 1, our main idea is to design a new pruning algorithm for neural networks in side-channel attacks by leveraging iterative pruning. Compared to single-shot pruning proposed in Year 3, iterative pruning can further optimize the size of neural networks by gradually pruning a neural network with multiple iterations but still being able to recover encryption keys. We will implement the proposed method and conduct evaluations by examining both power and EM (electromagnetic) traces on multiple targets, including microcontrollers (8-bit AVR XMEGA and 32-bit ARM STM32F3) and FPGAs (Xilinx Artix-7), running AES-128 encryption using ChipWhisperer platform. The performance of pruned neural networks will also be tested on Raspberry Pi and Nvidia Jetson. In Task 2, we will apply neural networks to simulated traces generated at the RTL level and examine the advantages and disadvantages of deep learning side-channel attacks. We will generate simulated traces from a hardware Verilog implementation of AES (SecWorks-AES [1]) and compare the attack results over these simulated traces between traditional attacks (Test Vector Leakage Assessment, Correlation Power Analysis, Template Attacks) and deep learning side-channel attacks.

Project Goals. The proposed tasks in Year 4 contribute to the two following goals: (1) enhancing the effectiveness and portability of neural networks for side-channel analysis; (2) detecting side-channel leakage at the design stage with neural networks.