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Defense-In-Depth approach for Detection and Mitigation of malicious hardware trojans in ASIC design for AI/ML Accelerators

Project ID:

P22_24

Principal Investigator:

Dr. Rashmi Jha

Co-Principal Investigator(s):

Dr. Marty Emmert, Dr. Houman Homayoun

Topic Areas:

Identify defenses to malicious insertion of design features during Digital ASIC design, Comparison of Asynchronous Logic vs Compute In/Near-Memory as Side-Channel Mitigations.

Abstract

Artificial Intelligence (AI) has revolutionized various industries, leading to the emergence of specialized ASIC designs optimized for AI/Machine Learning (ML) workloads. Hardware Trojans can be introduced into AI/ML accelerators during the design, fabrication, assembly, or testing stages. Adversaries can exploit the complex nature of DNN accelerator designs, such as their multiple cores and complex interconnects, to introduce subtle malicious modifications that can go undetected during manufacturing tests. Once a hardware Trojan is activated, it can perform a variety of malicious activities, such as leaking sensitive data or disrupting the normal functioning of the accelerator. In conclusion, the threat of hardware Trojans in DNN accelerators poses a serious risk to the security and reliability of systems that rely on these devices. It is crucial to implement robust security measures throughout the design, manufacturing, and operation phases to detect and prevent any malicious modifications that may compromise the integrity of the system, and in this project we take a wholistic defense-in-depth approach to detecting and mitigating Hardware Trojans in AI/ML ASICs using Side-channel analysis, Formal verification, Post-fabrication testing, Supply chain security, Hardware redundancy, Design-for-trust and Machine learning-based techniques.

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