Machine learning (ML) models face security vulnerabilities from both software and hardware attacks. While significant research has focused on digital hardware security, analog computing presents a promising yet relatively unexplored frontier due to its superior power and area efficiency. This project investigates security challenges and mitigation strategies for analog ML hardware architecture and data processing. System-level modeling tools will be developed to analyze analog ML architectures, incorporating transient power modeling for side-channel security analysis. Mitigation strategies include Analog Domain Oriented Masking (A-DOM) to introduce randomness in computational operations and charge equalization techniques to balance pattern dependent power consumption. Additionally, we propose analog data locking techniques leveraging phase alignment in the switching network, where only the correct key application ensures proper circuit functionality while incorrect keys induce circuit malfunction. This research will advance understanding and strategies for securing analog ML hardware and data processing against diverse cyber threats.