Proposed Tasks. Built upon the research findings of this project in Year 1, this research project in Year 2 (2024 - 2025) proposes to develop a new method to automatically detect lines in RISC-V assembly code that are vulnerable under hardware attacks, specifically fault injection attacks.

A fault injection attack, also known as glitching attack, is a physical attack on data and behavior of an embedded device by changing the voltage, temperature or electromagnetic radiation. To mitigate fault injection attacks, one effective way at the software level during the development stage is to write secure code that is more resilient against the attacks.

The team has previously developed methods/tools that can automatically detect vulnerable patterns (associated with fault injection attacks) in C and Arm assembly. In this proposed project, the team will expand our existing research to detect 4 vulnerable patterns, specifically in RISC-V assembly. Our main idea is to (1) parse the assembly code based on each line, (2) generate tokens based on registers and instructions, and (3) detect vulnerable patterns based on token matching across multiple lines. The team will design a customized parser for RISC-V assembly code and develop specific rules to identify each of the four vulnerable patterns. A dataset of RISC-V assembly files will be generated and labeled for evaluation. The dataset, source code, and publications will be shared with CHEST partners.

Project Goals. The overarching goal of this multi-year project is to promote the security and resilience of embedded systems against hardware attacks by minimizing vulnerabilities at the software level. Programmers can leverage these proposed methods to minimize hardware-related vulnerabilities in source code at the development stage.