validate and enhance their security. Reverse engineering to the highest possible level of abstraction is necessary since legacy systems’ HDL models are usually not available. This project focusses on functional reverse engineering or specification discovery which is the process of extracting an RTL model from an LUT-level netlist (which in turn is extracted from a FPGA bit-stream). This 2-year project was divided into five tasks:

• Task 1: Enhance and integrate multiple methods to identify word-level data path modules in LUT netlists. (Year 1)

• Task 2: Develop new methods to eliminate false positives and overlaps to increase accuracy. (Years 1, 2)

• Task 3: Develop specialized functional reverse engineering methods for DSP slices and multi-port BlockRAM memory units. (DSP slices – Year1, BlockRAMs – Year 2)

• Task 4: Develop an RTL model extraction methodology and tool flow based on these point algorithms. (Years 1, 2)

• Task 5: Evaluate and demonstrate the tool flow on practical FPGA designs. (Years 1, 2)

This project was proposed and approved as a 2-year project in 2023. The original project proposal is attached as an appendix for ready reference. Overall project background, motivation, goals, technical approach, tasks and schedule are described in it.

First year of the project commenced on 9/1/2023, coinciding with our academic year. We are in the 8th month since the beginning and are on track to complete the 1st year goals by 8/31/2024.

The rest of this proposal reports the progress achieved so far during the 1st year and describes the remaining work to be performed by the team to complete the project in two years as originally proposed.