Logic synthesis plays a vital role in chip design by converting high-level circuit descriptions into

optimized gate-level implementations and helps to bridge the gap between high-level synthesis and physical design [1]. Verification is a critical step in logic synthesis that ensures internal functionality, prevents costly errors, and reduces the time-to-market by identifying and fixing issues early in the design cycle [2]. However, traditional verification methods are computationally demanding and increasingly time-consuming, especially for complex designs [3,4]. For example, as measured in [5], the verification process takes more than 1 hour for the 128-bit multiplier utilizing ripple carry adder, and more than 100 hours for the booth multiplier, using the OneSpin commercial equivalence checker tool. Furthermore, using formal verification 1024-bit CSA multiplier takes 38093.78 seconds, using the open-source ABC [6] tool, on AMD EPYC 7543 32-Core processor

and an NVIDIA A100-SXM 80 GB.