Proposed Tasks. This research project (2025-2026) proposes to develop a new method to automatically detect key signals/variables in hardware designs written in Hardware Description Language (e.g., Verilog) at the Register Transfer Level (RTL). A Large Language Model will be utilized to perform the proposed detection automatically. Our proposed Large Language Model will be a standalone tool, which can be trained, customized, and queried locally for our IAB members. The proposed model is also static, meaning the detection is based on semantics in Verilog code and does not need to run simulations over hardware design.

Project Goals. Our proposed method aims to help the verification team automatically identify signals and variables that can lead to security vulnerabilities in hardware design, and therefore, reduces the amount of time that the verification team needs to spend. It aims to enrich and complement existing verification methods. If the proposed method is successful at the RTL level, we plan to further extend the detection to the netlist level in the future. The overarching goal of this project is to promote the security of hardware design during the design and verification stage.