This research aims to develop synthesis algorithms for secure and efficient polymorphic logic circuits. Polymorphic gates can implement multiple Boolean functions where the functionality is determined statically or dynamically based on internal/external control signals. A polymorphic circuit consists of both polymorphic gates and traditional monomorphic gates. Polymorphic circuits promise significant area, power, performance, and security advantages over conventional logic circuits. Each of these benefits have been demonstrated in recent years on small circuits via simulation/analytical studies and selective implementations. However, for a comprehensive evaluation and demonstration of these benefits for larger, more practical circuits, it is essential to develop synthesis methods to automatically generate polymorphic logic circuits from RTL descriptions while exploring PPA1 and security tradeoffs.

This project was proposed and approved as a 2-year project in 2024. The original project proposal is attached as an appendix for ready reference. Overall project background, motivation, goals, technical approach, tasks and schedule are described in it.

First year of the project commenced on 9/1/2024, coinciding with our academic year. We are in the 7th month since the beginning and are on track to complete the 1st year goals by 8/31/2025.

The rest of this proposal reports the progress achieved so far during the 1st year and describes the remaining work to be performed by the team to complete the project in two years as originally proposed.